AMD Zeppelin SOC Architecture Announced At ISSCC 2018, Full Specs Detailed
AMD has officially announced the latest specifics about its Zeppelin SOC for multi-chip architectures during the International Solid-State Circuits Conference (ISSCC) 2018. The Zeppelin SOC is the moniker for the die that is utilized on the entire variety of AMD 14nm chips, which includes Ryzen, Ryzen Threadripper, and EPYC families.
AMD Zeppelin SOC Architecture Background Information
The AMD Zeppelin SOC Architecture was designed to supply several market sections while being performance and power competent. It has been known that those objectives were achieved by AMD. This also helps the American multi-national company to go back to the fight in the CPU market alongside Intel.
It is worth noting that the Zeppelin die was composed of two Core Complexes. For a quick reference, a core complex was the foundation of the Zeppelin die and it’s comprised four Zen cores and their connected L2 / L3 cache. There are three products that are equipped with the Zeppelin die, these include 4-die multi-chip module (MCM) for Server, 2-die multi-chip module (MCM) for High-End Desktop and the 1-die multi-chip module (MCM) for Desktop.
AMD Zeppelin SOC Architecture Specs
When it comes to specs, each of the Zeppelin dies is composed of 8 Zen x86 cores and all of the devices released up to date are based on the first generation Zen core architecture which utilizes the 14nm process node. The cores have the right to use 4 MB of L2 cache and 16 MB of L3 cache overall. As for the memory side, each Zeppelin dies can provide 2 channel DDR4 with ECC support permitting 2 DIMMs per channel for an all-out of 256 GB aptitude per channel (EPYC).
Additionally, each die is comprised of a large interconnected network composed of the Infinity Fabric and Coherent connect links. Also, each of the Zeppelin dies delivers 32 high-speed I/O lanes which for Threadripper are 64 PCIe over-all and for EPYC that’s 128 PCIe lanes.
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